Shimeng Yu

Active 2010–2026

306
Papers
25,294
Citations
66
h-index
183
i10-index

Citations

Citations per year for Shimeng Yu1983: 1 citations1987: 2 citations2003: 3 citations2011: 17 citations2012: 47 citations2013: 97 citations2014: 134 citations2015: 258 citations2016: 409 citations2017: 477 citations2018: 773 citations2019: 1,179 citations2020: 1,518 citations2021: 1,660 citations2022: 1,742 citations2023: 1,636 citations2024: 1,699 citations2025: 1,261 citations2026: 243 citations1984–1986: no citations, so these years are not shown1988–2002: no citations, so these years are not shown2004–2010: no citations, so these years are not shown

Citation sources

Countries

World map of the countries and regions citing this authorChina: 2,592 citing papers, 25.5% of this breakdownUnited States: 2,435 citing papers, 23.9% of this breakdownSouth Korea: 911 citing papers, 8.9% of this breakdownGermany: 481 citing papers, 4.7% of this breakdownSingapore: 357 citing papers, 3.5% of this breakdownIndia: 343 citing papers, 3.4% of this breakdownTaiwan: 316 citing papers, 3.1% of this breakdownUnited Kingdom: 252 citing papers, 2.5% of this breakdownItaly: 247 citing papers, 2.4% of this breakdownHong Kong: 242 citing papers, 2.4% of this breakdownFrance: 210 citing papers, 2.1% of this breakdownJapan: 189 citing papers, 1.9% of this breakdown
0%25.5%Other 15.7%

Fields

  • Engineering81.1%
  • Computer Science15.6%
  • Physics and Astronomy0.9%
  • Neuroscience0.7%
  • Materials Science0.6%
  • Medicine0.3%
  • Other0.8%

Topics

  • Advanced Memory and Neural Computing28.5%
  • Ferroelectric and Negative Capacitance Devices15.6%
  • Neuroscience and Neural Engineering8.2%
  • Photoreceptor and optogenetics research4.6%
  • Neural Networks and Reservoir Computing4.5%
  • Semiconductor materials and devices3.9%
  • Other34.7%

Coauthors

All papers

Open in search
  1. Optoelectronic resistive random access memory for neuromorphic vision sensors

    Authors: , , , , , , , , , , - Nature Nanotechnology 2019 cited by 1,285

  2. Neuro-inspired computing chips

    Authors: , , , , , , , , - Nature Electronics 2020 cited by 874

  3. Compute-in-Memory Chips for Deep Learning: Recent Trends and Prospects

    Authors: , , , , - IEEE Circuits and Systems Magazine 2021 cited by 359

  4. NeuroSim: A Circuit-Level Macro Model for Benchmarking Neuro-Inspired Architectures in Online Learning

    Authors: , , - IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 2018 cited by 632

  5. Metal-Oxide RRAM

    Authors: , , , , , , , , - IEEE, Proc. IEEE 2012 cited by 2,665

  6. Neuro-Inspired Computing With Emerging Nonvolatile Memorys

    Authors: - IEEE, Proc. IEEE 2018 cited by 1,118

  7. DNN+NeuroSim: An End-to-End Benchmarking Framework for Compute-in-Memory Accelerators with Versatile Device Technologies

    Authors: , , , , - IEEE International Electron Devices Meeting (IEDM) 2019 cited by 341

  8. Power-efficient combinatorial optimization using intrinsic noise in memristor Hopfield neural networks

    Authors: , , , , , , , , , , , , , - Nature Electronics 2020 cited by 397

  9. Synaptic electronics: materials, devices and applications

    Authors: , , - Nanotechnology 2013 cited by 1,244

  10. A Twin-8T SRAM Computation-in-Memory Unit-Macro for Multibit CNN-Based AI Edge Processors

    Authors: , , , , , , , , , , , , , , , - IEEE Journal of Solid-State Circuits, IEEE J. Solid State Circuits 2019 cited by 220

  11. SiGe epitaxial memory for neuromorphic computing with reproducible high performance based on engineered dislocations

    Authors: , , , , , , , , - Nature Materials 2018 cited by 685

  12. NeuroSim+: An integrated device-to-algorithm framework for benchmarking synaptic devices and array architectures

    Authors: , , - IEEE International Electron Devices Meeting (IEDM) 2017 cited by 421

  13. RRAM for Compute-in-Memory: From Inference to Training

    Authors: , , , - IEEE Transactions on Circuits and Systems I Regular Papers, IEEE Trans. Circuits Syst. I Regul. Pap. 2021 cited by 129

  14. A Compact Model for Metal–Oxide Resistive Random Access Memory With Experiment Verification

    Authors: , , , , , , - IEEE Transactions on Electron Devices 2016 cited by 263

  15. Emerging Memory Technologies: Recent Trends and Prospects

    Authors: , - IEEE Solid-State Circuits Magazine 2016 cited by 539

  16. Two-Way Transpose Multibit 6T SRAM Computing-in-Memory Macro for Inference-Training AI Edge Chips

    Authors: , , , , , , , , , , , , , , , , , , , , , , , , - IEEE Journal of Solid-State Circuits, IEEE J. Solid State Circuits 2021 cited by 69

  17. High-Throughput In-Memory Computing for Binary Deep Neural Networks With Monolithically Integrated RRAM and 90-nm CMOS

    Authors: , , , - IEEE Transactions on Electron Devices 2020 cited by 162

  18. 15.2 A 28nm 64Kb Inference-Training Two-Way Transpose Multibit 6T SRAM Compute-in-Memory Macro for AI Edge Chips

    Authors: , , , , , , , , , , , , , , , , , , , , , , - IEEE International Solid- State Circuits Conference - (ISSCC) 2020 cited by 181

  19. Compact Modeling of RRAM Devices and Its Applications in 1T1R and 1S1R Array Design

    Authors: , - IEEE Transactions on Electron Devices 2015 cited by 353

  20. Ferroelectric FET analog synapse for acceleration of deep neural network training

    Authors: , , , , , , - IEEE International Electron Devices Meeting (IEDM) 2017 cited by 571

  21. A 65nm 4Kb algorithm-dependent computing-in-memory SRAM unit-macro with 2.3ns and 55.8TOPS/W fully parallel product-sum operation for binary DNN edge processors

    Authors: , , , , , , , , , , - IEEE International Solid - State Circuits Conference - (ISSCC) 2018 cited by 245

  22. Optimizing Weight Mapping and Data Flow for Convolutional Neural Networks on Processing-in-Memory Architectures

    Authors: , , - IEEE Transactions on Circuits and Systems I Regular Papers, IEEE Trans. Circuits Syst. I Fundam. Theory Appl. 2019 cited by 98

  23. A Twin-8T SRAM Computation-In-Memory Macro for Multiple-Bit CNN-Based Machine Learning

    Authors: , , , , , , , , , , , , , , , - IEEE International Solid- State Circuits Conference - (ISSCC) 2019 cited by 252

  24. A Dual-Split 6T SRAM-Based Computing-in-Memory Unit-Macro With Fully Parallel Product-Sum Operation for Binarized DNN Edge Processors

    Authors: , , , , , , , , , - IEEE Transactions on Circuits and Systems I Regular Papers, IEEE Trans. Circuits Syst. I Regul. Pap. 2019 cited by 150