Shimeng Yu
Active 2010–2026
- 306
- Papers
- 25,294
- Citations
- 66
- h-index
- 183
- i10-index
Citations
Citation sources
Countries
Institutions
Fields
- Engineering81.1%
- Computer Science15.6%
- Physics and Astronomy0.9%
- Neuroscience0.7%
- Materials Science0.6%
- Medicine0.3%
- Other0.8%
Topics
- Advanced Memory and Neural Computing28.5%
- Ferroelectric and Negative Capacitance Devices15.6%
- Neuroscience and Neural Engineering8.2%
- Photoreceptor and optogenetics research4.6%
- Neural Networks and Reservoir Computing4.5%
- Semiconductor materials and devices3.9%
- Other34.7%
Coauthors
- Xiaochen Peng47
- Pai-Yu Chen36
- Jae-sun Seo29
- Suman Datta29
- Xiaoyu Sun29
- Anni Lu28
- Rui Liu28
- Hongwu Jiang27
- Yandong Luo27
- Shanshi Huang25
- H.‐S. Philip Wong24
- Wantong Li23
- Bin Gao20
- Yu Cao20
- Asif Islam Khan17
- Yuan-Chun Luo17
- Huaqiang Wu16
- Po-Kai Hsu16
- He Qian15
- Meng-Fan Chang15
- Faaiq G. Waqar14
- Junmo Lee13
- Wonbo Shim12
- Janak Sharda11
All papers
- Optoelectronic resistive random access memory for neuromorphic vision sensors
Authors: Feichi Zhou, Zheng Zhou, Jiewei Chen, Tsz Hin Choy, Jingli Wang, Ning Zhang, Ziyuan Lin, Shimeng Yu, Jinfeng Kang, H.‐S. Philip Wong, Yang Chai - Nature Nanotechnology 2019 cited by 1,285
- Neuro-inspired computing chips
Authors: Wenqiang Zhang, Bin Gao, Jianshi Tang, Peng Yao, Shimeng Yu, Meng‐Fan Chang, Hoi‐Jun Yoo, He Qian, Huaqiang Wu - Nature Electronics 2020 cited by 874
- Compute-in-Memory Chips for Deep Learning: Recent Trends and Prospects
Authors: Shimeng Yu, Hongwu Jiang, Shanshi Huang, Xiaochen Peng, Anni Lu - IEEE Circuits and Systems Magazine 2021 cited by 359
- NeuroSim: A Circuit-Level Macro Model for Benchmarking Neuro-Inspired Architectures in Online Learning
Authors: Pai-Yu Chen, Xiaochen Peng, Shimeng Yu - IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 2018 cited by 632
- Metal-Oxide RRAM
Authors: H.-S. Philip Wong, Heng-Yuan Lee, Shimeng Yu, Yu-Sheng Chen, Yi Wu, Pang-Shiu Chen, Byoungil Lee, Frederick T. Chen, Ming-Jinn Tsai - IEEE, Proc. IEEE 2012 cited by 2,665
- Neuro-Inspired Computing With Emerging Nonvolatile Memorys
Authors: Shimeng Yu - IEEE, Proc. IEEE 2018 cited by 1,118
- DNN+NeuroSim: An End-to-End Benchmarking Framework for Compute-in-Memory Accelerators with Versatile Device Technologies
Authors: Xiaochen Peng, Shanshi Huang, Yandong Luo, Xiaoyu Sun, Shimeng Yu - IEEE International Electron Devices Meeting (IEDM) 2019 cited by 341
- Power-efficient combinatorial optimization using intrinsic noise in memristor Hopfield neural networks
Authors: Fuxi Cai, Suhas Kumar, Thomas Van Vaerenbergh, Xia Sheng, Rui Liu, Can Li, Zhan Liu, Martin Foltín, Shimeng Yu, Qiangfei Xia, J. Joshua Yang, Raymond G. Beausoleil, Wei Lü, John Paul Strachan - Nature Electronics 2020 cited by 397
- Synaptic electronics: materials, devices and applications
Authors: Duygu Kuzum, Shimeng Yu, H-S Philip Wong - Nanotechnology 2013 cited by 1,244
- A Twin-8T SRAM Computation-in-Memory Unit-Macro for Multibit CNN-Based AI Edge Processors
Authors: Xin Si, Rui Liu, Shimeng Yu, Ren-Shuo Liu, Chih-Cheng Hsieh, Kea-Tiong Tang, Qiang Li, Meng-Fan Chang, Jia-Jing Chen, Yung-Ning Tu, Wei-Hsing Huang, Jing-Hong Wang, Yen-Cheng Chiu, Wei-Chen Wei, Ssu-Yen Wu, Xiaoyu Sun - IEEE Journal of Solid-State Circuits, IEEE J. Solid State Circuits 2019 cited by 220
- SiGe epitaxial memory for neuromorphic computing with reproducible high performance based on engineered dislocations
Authors: Shinhyun Choi, Scott H. Tan, Zefan Li, Yunjo Kim, Chanyeol Choi, Pai-Yu Chen, Han‐Wool Yeon, Shimeng Yu, Jeehwan Kim - Nature Materials 2018 cited by 685
- NeuroSim+: An integrated device-to-algorithm framework for benchmarking synaptic devices and array architectures
Authors: Pai-Yu Chen, Xiaochen Peng, Shimeng Yu - IEEE International Electron Devices Meeting (IEDM) 2017 cited by 421
- RRAM for Compute-in-Memory: From Inference to Training
Authors: Shimeng Yu, Wonbo Shim, Xiaochen Peng, Yandong Luo - IEEE Transactions on Circuits and Systems I Regular Papers, IEEE Trans. Circuits Syst. I Regul. Pap. 2021 cited by 129
- A Compact Model for Metal–Oxide Resistive Random Access Memory With Experiment Verification
Authors: Zizhen Jiang, Yi Wu, Shimeng Yu, Lin Yang, Kay Song, Zia Karim, H.‐S. Philip Wong - IEEE Transactions on Electron Devices 2016 cited by 263
- Emerging Memory Technologies: Recent Trends and Prospects
Authors: Shimeng Yu, Pai-Yu Chen - IEEE Solid-State Circuits Magazine 2016 cited by 539
- Two-Way Transpose Multibit 6T SRAM Computing-in-Memory Macro for Inference-Training AI Edge Chips
Authors: Jian-Wei Su, Xin Si, Yen-Chi Chou, Ting-Wei Chang, Wei-Hsing Huang, Yung-Ning Tu, Ruhui Liu, Pei-Jung Lu, Ta-Wei Liu, Jing-Hong Wang, Yen-Lin Chung, Jin-Sheng Ren, Fu-Chun Chang, Yuan Wu, Hongwu Jiang, Shanshi Huang, Sih-Han Li, Shyh-Shyuan Sheu, Chih-I Wu, Chung-Chuan Lo, Ren-Shuo Liu, Chih-Cheng Hsieh, Kea-Tiong Tang, Shimeng Yu, Meng-Fan Chang - IEEE Journal of Solid-State Circuits, IEEE J. Solid State Circuits 2021 cited by 69
- High-Throughput In-Memory Computing for Binary Deep Neural Networks With Monolithically Integrated RRAM and 90-nm CMOS
Authors: Shihui Yin, Xiaoyu Sun, Shimeng Yu, Jae-sun Seo - IEEE Transactions on Electron Devices 2020 cited by 162
- 15.2 A 28nm 64Kb Inference-Training Two-Way Transpose Multibit 6T SRAM Compute-in-Memory Macro for AI Edge Chips
Authors: Jian-Wei Su, Xin Si, Yen-Chi Chou, Ting-Wei Chang, Wei-Hsing Huang, Yung-Ning Tu, Ruhui Liu, Pei-Jung Lu, Ta-Wei Liu, Jing-Hong Wang, Zhixiao Zhang, Hongwu Jiang, Shanshi Huang, Chung-Chuan Lo, Ren-Shuo Liu, Chih-Cheng Hsieh, Kea-Tiong Tang, Shyh-Shyuan Sheu, Sih-Han Li, Heng-Yuan Lee, Shih-Chieh Chang, Shimeng Yu, Meng-Fan Chang - IEEE International Solid- State Circuits Conference - (ISSCC) 2020 cited by 181
- Compact Modeling of RRAM Devices and Its Applications in 1T1R and 1S1R Array Design
Authors: Pai-Yu Chen, Shimeng Yu - IEEE Transactions on Electron Devices 2015 cited by 353
- Ferroelectric FET analog synapse for acceleration of deep neural network training
Authors: Matthew Jerry, Pai-Yu Chen, Jianchi Zhang, Pankaj Sharma, Kai Ni, Shimeng Yu, Suman Datta - IEEE International Electron Devices Meeting (IEDM) 2017 cited by 571
- A 65nm 4Kb algorithm-dependent computing-in-memory SRAM unit-macro with 2.3ns and 55.8TOPS/W fully parallel product-sum operation for binary DNN edge processors
Authors: Win-San Khwa, Jia-Jing Chen, Jia-Fang Li, Xin Si, En-Yu Yang, Xiaoyu Sun, Rui Liu, Pai-Yu Chen, Qiang Li, Shimeng Yu, Meng-Fan Chang - IEEE International Solid - State Circuits Conference - (ISSCC) 2018 cited by 245
- Optimizing Weight Mapping and Data Flow for Convolutional Neural Networks on Processing-in-Memory Architectures
Authors: Xiaochen Peng, Rui Liu, Shimeng Yu - IEEE Transactions on Circuits and Systems I Regular Papers, IEEE Trans. Circuits Syst. I Fundam. Theory Appl. 2019 cited by 98
- A Twin-8T SRAM Computation-In-Memory Macro for Multiple-Bit CNN-Based Machine Learning
Authors: Xin Si, Jia-Jing Chen, Yung-Ning Tu, Wei-Hsing Huang, Jing-Hong Wang, Yen-Cheng Chiu, Wei-Chen Wei, Ssu-Yen Wu, Xiaoyu Sun, Rui Liu, Shimeng Yu, Ren-Shuo Liu, Chih-Cheng Hsieh, Kea-Tiong Tang, Qiang Li, Meng-Fan Chang - IEEE International Solid- State Circuits Conference - (ISSCC) 2019 cited by 252
- A Dual-Split 6T SRAM-Based Computing-in-Memory Unit-Macro With Fully Parallel Product-Sum Operation for Binarized DNN Edge Processors
Authors: Xin Si, Win-San Khwa, Jia-Jing Chen, Jia-Fang Li, Xiaoyu Sun, Rui Liu, Shimeng Yu, Hiroyuki Yamauchi, Qiang Li, Meng-Fan Chang - IEEE Transactions on Circuits and Systems I Regular Papers, IEEE Trans. Circuits Syst. I Regul. Pap. 2019 cited by 150
