Equalization and Clock and Data Recovery Techniques for 10-Gb/s CMOS Serial-Link Receivers
Two equalizer filter topologies and a merged equalizer/CDR circuit are described that operate at 10 Gb/s in 0.13-mum CMOS technology. Using techniques such as reverse scaling, passive peaking networks, and dual- and triple-loop adaptation, the prototypes adapt to FR4 trace lengths up to 24 inches. The equalizer/CDR circuit retimes the data with a bit error rate of 10 -13 while consuming 133 mW from a 1.6-V supply.