A 5 V-only 256 kbit CMOS flash EEPROM

Authors: S. D'Arrigo, G. Imondi, G. Santin, Michael Gill, R. Cleavelin, S. Spagliccia, E. Tomassetti, Siqi Lin, Anh Van Nguyen, P. Shah, Giuseppe Savarese, D. McElroy - IEEE International Solid-State Circuits Conference 2003 cited by 29

The authors describe a 256-kbit flash EEPROM (electrically erasable and programmable read-only memory) device which requires only 5 V for program, erase, and read operations and has performance and cost comparable to that of the recently reported dual-power-supply flash EEPROMs, which require 12 V for programming and erase and 5 V for read. The memory cell consists of a floating-gate transistor and a merged-pass-gate transistor. The process is array-contactless EEPROM (ACEE), with buried source/drain for the bit lines with a tunnel oxide module and a 20-V CMOS module. The program and erase operations employ the Fowler-Nordheim current tunneled through 100-AA oxide when the proper electrical voltages are applied to the selected bit. The device and technology parameters are summarized.< >