27.8 A static contention-free single-phase-clocked 24T flip-flop in 45nm for low-power applications

著者: Yejoong Kim, Wanyeong Jung, Inhee Lee, Qing Dong, Michael B. Henry, Dennis Sylvester, David T. Blaauw - 2014 IEEE International Solid-State Circuits Conference Digest of Technical Papers (ISSCC) 2014 被引用: 87

Near-threshold computing (NTC) is an attractive solution to stagnating energy efficiencies in digital integrated circuits, arising from slowed voltage scaling in nanometer CMOS [1-2]. The design of sequential elements for NTC, as well as in voltage-scaled systems operating at both near-threshold and super-threshold, has not been extensively studied. However, it is well known that sequential elements have a strong sensitivity to process variations in NTC [2], which can have a significant impact on system yield and power consumption. In order to achieve reliable energy-efficient operation across a wide operating voltage range, a flip-flop should have the following attributes: 1) static operation, since dynamic nodes are highly susceptible to PVT variations at low voltage; 2) contention-free transitions, since ratioed logic has poor robustness across the wide range of device I ON /I OFF ratios incurred with voltage scaling; 3) single-phase clocking, which avoids toggling of internal clock inverters and the corresponding power penalty; 4) minimum or no area penalty compared to conventional flip-flops.