著者: T. Saeki, Y. Nakaoka, M. Fujita, A. Tanaka, K. Nagata, Keiichiro SAKAKIBARA, T. Matano, Yuuji HOSHINO, K. Miyano, S. Isa, E. Kakehashi, J.M. Drynan, M. Komuro, T. Fukase, H. Iwasaki, J. Sekine, M. Igeta, N. Nakanishi, T. Itani, Kodai YOSHIDA, H. Yoshino, S. Hashimoto, T. Yoshii, M. Ichinose, T. Imura, M. Uziie, K. Koyama, Y. Fukuzo, T. Okuda - 1996 IEEE International Solid-State Circuits Conference. Digest of TEchnical Papers, ISSCC 2002 被引用: 35
A 245.7 mm/sup 2/ 256 Mb SDRAM uses: (1) 60.2% cell-occupancy ratio array, (2) prefetched pipeline using first-in first-out buffer with parallel/serial converter, (3) synchronous mirror delay circuit.
