On the verification of synthesized designs using automatically generated transformational witnesses

著者: Elena Teica, Rajesh Radhakrishnan, Ranga Vemuri - Design, Automation & Test in Europe Conference, DATE 2001 被引用: 0

Summary form only given. The authors present a new methodology for verifying the synthesized designs, and for debugging the software implementation of high-level synthesis algorithms. The methodology is based on a a set of 7 RTL transformations which are able to emulate the effect of many scheduling and resource allocation algorithms.