Robert K. Brayton

Active 1963–2024

347
Papers
22,574
Citations
70
h-index
251
i10-index

Citations

Citations per year for Robert K. Brayton1965: 2 citations1968: 1 citations1969: 2 citations1970: 1 citations1971: 5 citations1972: 11 citations1973: 12 citations1974: 6 citations1975: 8 citations1976: 7 citations1977: 7 citations1978: 4 citations1979: 2 citations1980: 9 citations1981: 22 citations1982: 11 citations1983: 14 citations1984: 19 citations1985: 37 citations1986: 36 citations1987: 45 citations1988: 124 citations1989: 152 citations1990: 231 citations1991: 335 citations1992: 430 citations1993: 461 citations1994: 513 citations1995: 626 citations1996: 512 citations1997: 485 citations1998: 456 citations1999: 478 citations2000: 471 citations2001: 411 citations2002: 473 citations2003: 498 citations2004: 445 citations2005: 379 citations2006: 486 citations2007: 400 citations2008: 421 citations2009: 449 citations2010: 374 citations2011: 418 citations2012: 307 citations2013: 341 citations2014: 313 citations2015: 375 citations2016: 312 citations2017: 292 citations2018: 384 citations2019: 367 citations2020: 302 citations2021: 307 citations2022: 226 citations2023: 283 citations2024: 283 citations2025: 277 citations2026: 86 citations1966–1967: no citations, so these years are not shown

Citation sources

Countries

World map of the countries and regions citing this authorUnited States: 4,458 citing papers, 37.9% of this breakdownGermany: 1,032 citing papers, 8.8% of this breakdownItaly: 566 citing papers, 4.8% of this breakdownChina: 484 citing papers, 4.1% of this breakdownJapan: 476 citing papers, 4% of this breakdownUnited Kingdom: 470 citing papers, 4% of this breakdownCanada: 456 citing papers, 3.9% of this breakdownFrance: 361 citing papers, 3.1% of this breakdownTaiwan: 339 citing papers, 2.9% of this breakdownSwitzerland: 288 citing papers, 2.4% of this breakdownNetherlands: 278 citing papers, 2.4% of this breakdownIndia: 237 citing papers, 2% of this breakdown
0%37.9%Other 19.7%

Fields

  • Computer Science69.8%
  • Engineering24%
  • Neuroscience1.6%
  • Biochemistry, Genetics and Molecular Biology1.5%
  • Mathematics0.8%
  • Physics and Astronomy0.6%
  • Other1.7%

Topics

  • Formal Methods in Verification14%
  • VLSI and Analog Circuit Testing10.5%
  • Low-power high-performance VLSI design7.8%
  • VLSI and FPGA Design Techniques6.4%
  • Embedded Systems Design Techniques6.1%
  • Software Testing and Debugging Techniques3.8%
  • Other51.4%

Coauthors

All papers

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  1. ABC: An Academic Industrial-Strength Verification Tool

    Authors: , - Lecture notes in computer science, CAV 2010 cited by 923

  2. DAG-aware AIG rewriting a fresh look at combinational logic synthesis

    Authors: , , - Proceedings - ACM IEEE Design Automation Conference, DAC 2006 cited by 484

  3. Logic Minimization Algorithms for VLSI Synthesis

    Authors: , , , - Kluwer international series in engineering and computer science 1984 cited by 1,974

  4. A Simulation-Guided Paradigm for Logic Synthesis and Verification

    Authors: , , , , - IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 2021 cited by 36

  5. Reducing Structural Bias in Technology Mapping

    Authors: , , , , - ICCAD-2005. IEEE/ACM International Conference on Computer-Aided Design 2005 cited by 82

  6. Scalable don't-care-based logic optimization and resynthesis

    Authors: , , , - ACM Transactions on Reconfigurable Technology and Systems, ACM Trans. Reconfigurable Technol. Syst. 2009 cited by 91

  7. Verifying Continuous Time Markov Chains

    Authors: , , , - Lecture notes in computer science, CAV 1996 cited by 340

  8. Improvements to Technology Mapping for LUT-Based FPGAs

    Authors: , , - IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, FPGA 2006 cited by 156

  9. Efficient implementation of property directed reachability

    Authors: , , - http://www.eecs.berkeley.edu/%7Ealanmi/publications/2011/fmcad11_pdr.pdf 2011 cited by 276

  10. A theory of nonlinear networks. I

    Authors: , - Quarterly of Applied Mathematics 1964 cited by 455

  11. Improvements to combinational equivalence checking

    Authors: , , , - Digest of technical papers/Digest of technical papers - IEEE/ACM International Conference on Computer-Aided Design, ICCAD 2006 cited by 130

  12. Scalable Logic Synthesis using a Simple Circuit Structure

    Authors: , - Ground Water 2006 cited by 87

  13. MIS: A Multiple-Level Logic Optimization System

    Authors: , , , - IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 1987 cited by 1,163

  14. Model-checking continous-time Markov chains

    Authors: , , , - ACM Transactions on Computational Logic, ACM Trans. Comput. Log. 2000 cited by 415

  15. Multilevel logic synthesis

    Authors: , , - IEEE, Proc. IEEE 1990 cited by 412

  16. SAT-Based Complete Don't-Care Computation for Network Optimization

    Authors: , - Design, Automation, and Test in Europe, DATE 2005 cited by 98

  17. Deep Integration of Circuit Simulator and SAT Solver

    Authors: , , , , - 58th ACM/IEEE Design Automation Conference (DAC) 2021 cited by 17

  18. Enabling exact delay synthesis

    Authors: , , , , , , , , - IEEE/ACM International Conference on Computer-Aided Design (ICCAD) 2017 cited by 17

  19. Enhancing Delay-Driven LUT Mapping With Boolean Decomposition

    Authors: , , , - IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 2024 cited by 6

  20. Sequential Circuit Design Using Synthesis and Optimization

    Authors: , , , , , - Proceedings 1992 IEEE International Conference on Computer Design: VLSI in Computers & Processors, ICCD 1992 cited by 615

  21. Logic verification using binary decision diagrams in a logic synthesis environment

    Authors: , , , - [1988] IEEE International Conference on Computer-Aided Design (ICCAD-89) Digest of Technical Papers 1988 cited by 509

  22. Multi-level logic minimization using implicit don't cares

    Authors: , , , , , , , - IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 1988 cited by 264

  23. Global delay optimization using structural choices

    Authors: , , - ACM/SIGDA international symposium on Field programmable gate arrays, FPGA 2010 cited by 31

  24. Improvements to boolean resynthesis

    Authors: , , , , , , , - Design, Automation & Test in Europe Conference & Exhibition (DATE) 2018 cited by 20