Sharad Malik

Active 1988–2026

277
Papers
18,714
Citations
60
h-index
175
i10-index

Citations

Citations per year for Sharad Malik1967: 1 citations1975: 1 citations1980: 1 citations1984: 1 citations1985: 1 citations1988: 4 citations1989: 4 citations1990: 13 citations1991: 32 citations1992: 40 citations1993: 54 citations1994: 73 citations1995: 129 citations1996: 146 citations1997: 198 citations1998: 191 citations1999: 274 citations2000: 293 citations2001: 266 citations2002: 418 citations2003: 516 citations2004: 698 citations2005: 724 citations2006: 683 citations2007: 704 citations2008: 625 citations2009: 575 citations2010: 587 citations2011: 459 citations2012: 472 citations2013: 479 citations2014: 413 citations2015: 405 citations2016: 418 citations2017: 432 citations2018: 432 citations2019: 470 citations2020: 410 citations2021: 372 citations2022: 286 citations2023: 267 citations2024: 261 citations2025: 193 citations2026: 81 citations1968–1974: no citations, so these years are not shown1976–1979: no citations, so these years are not shown1981–1983: no citations, so these years are not shown1986–1987: no citations, so these years are not shown

Citation sources

Countries

World map of the countries and regions citing this authorUnited States: 4,269 citing papers, 34.5% of this breakdownGermany: 1,077 citing papers, 8.7% of this breakdownFrance: 602 citing papers, 4.9% of this breakdownChina: 591 citing papers, 4.8% of this breakdownUnited Kingdom: 501 citing papers, 4.1% of this breakdownItaly: 480 citing papers, 3.9% of this breakdownCanada: 401 citing papers, 3.3% of this breakdownIndia: 351 citing papers, 2.8% of this breakdownSpain: 293 citing papers, 2.4% of this breakdownAustria: 289 citing papers, 2.3% of this breakdownJapan: 276 citing papers, 2.2% of this breakdownTaiwan: 215 citing papers, 1.7% of this breakdown
0%34.5%Other 24.4%

Fields

  • Computer Science87.9%
  • Engineering9.8%
  • Decision Sciences0.6%
  • Biochemistry, Genetics and Molecular Biology0.3%
  • Social Sciences0.2%
  • Business, Management and Accounting0.2%
  • Other1%

Topics

  • Formal Methods in Verification10.9%
  • Parallel Computing and Optimization Techniques9.1%
  • Embedded Systems Design Techniques8.6%
  • Interconnection Networks and Systems5.2%
  • VLSI and Analog Circuit Testing4.1%
  • Low-power high-performance VLSI design3.8%
  • Other58.3%

Coauthors

All papers

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  1. Evaluating the security of logic encryption algorithms

    Authors: , , - IEEE International Symposium on Hardware Oriented Security and Trust (HOST) 2015 cited by 772

  2. Chaff: Engineering an Efficient SAT Solver

    Authors: , , , , - Design Automation Conference (IEEE Cat. No.01CH37232), DAC 2001 cited by 2,904

  3. Boolean Satisfiability Solvers and Their Applications in Model Checking

    Authors: , , - IEEE, Proc. IEEE 2015 cited by 117

  4. On Solving the Partial MAX-SAT Problem

    Authors: , - Lecture notes in computer science, SAT 2006 cited by 265

  5. Conflict-Driven Clause Learning SAT Solvers

    Authors: , , - Frontiers in artificial intelligence and applications, Handbook of Satisfiability 2009 cited by 321

  6. Reverse Engineering Digital Circuits Using Structural and Functional Analyses

    Authors: , , , , , , , , - IEEE Transactions on Emerging Topics in Computing, IEEE Trans. Emerg. Top. Comput. 2014 cited by 139

  7. Morpheus: A Vulnerability-Tolerant Secure Architecture Based on Ensembles of Moving Target Defenses with Churn

    Authors: , , , , , , , , , , , , - Twenty-Fourth International Conference on Architectural Support for Programming Languages and Operating Systems, ASPLOS 2019 cited by 53

  8. Power analysis of embedded software: a first step towards software power minimization

    Authors: , , - IEEE Transactions on Very Large Scale Integration (VLSI) Systems, ICCAD 1994 cited by 997

  9. Malware detection using machine learning based analysis of virtual memory access patterns

    Authors: , , , - Design, Automation & Test in Europe Conference & Exhibition (DATE) 2017 cited by 125

  10. All-SAT Using Minimal Blocking Clauses

    Authors: , , , - 27th International Conference on VLSI Design and 2014 13th International Conference on Embedded Systems, VLSID 2014 cited by 38

  11. WordRev: Finding word-level structures in a sea of bit-level gates

    Authors: , , , , , , , - IEEE International Symposium on Hardware-Oriented Security and Trust (HOST) 2013 cited by 89

  12. Instruction-Level Abstraction (ILA): A Uniform Specification for System-on-Chip (SoC) Verification

    Authors: , , , , , - ACM Transactions on Design Automation of Electronic Systems, ACM Trans. Design Autom. Electr. Syst. 2018 cited by 42

  13. Propositional SAT Solving

    Authors: , - Handbook of Model Checking 2018 cited by 24

  14. Lazy Self-composition for Security Verification

    Authors: , , , , - Lecture notes in computer science, CAV (2) 2018 cited by 19

  15. Boolean satisfiability from theoretical hardness to practical success

    Authors: , - Communications of the ACM, Commun. ACM 2009 cited by 169

  16. ILAng: A Modeling and Verification Platform for SoCs Using Instruction-Level Abstractions

    Authors: , , , - Lecture notes in computer science, TACAS (1) 2019 cited by 17

  17. Generalizing Tandem Simulation: Connecting High-level and RTL Simulation Models

    Authors: , , - 27th Asia and South Pacific Design Automation Conference (ASP-DAC) 2022 cited by 8

  18. Logic verification using binary decision diagrams in a logic synthesis environment

    Authors: , , , - [1988] IEEE International Conference on Computer-Aided Design (ICCAD-89) Digest of Technical Papers 1988 cited by 509

  19. Template-based Synthesis of Instruction-Level Abstractions for SoC Verification

    Authors: , , , - Formal Methods in Computer-Aided Design (FMCAD) 2015 cited by 32

  20. Predicting Serializability Violations: SMT-Based Search vs. DPOR-Based Search

    Authors: , , , - Lecture notes in computer science, Haifa Verification Conference 2011 cited by 17

  21. Synthesizing Environment Invariants for Modular Hardware Verification

    Authors: , , , , - Lecture notes in computer science, VMCAI 2020 cited by 13

  22. RTL Verification for Secure Speculation Using Contract Shadow Logic

    Authors: , , , , - International Conference on Architectural Support for Programming Languages and Operating Systems, Volume 1, ASPLOS (1) 2025 cited by 7

  23. Automatic Generation of Architecture-Level Models from RTL Designs for Processors and Accelerators

    Authors: , , - Design, Automation & Test in Europe Conference & Exhibition (DATE) 2022 cited by 7

  24. Security Verification of Low-Trust Architectures

    Authors: , , , , , , - SIGSAC Conference on Computer and Communications Security, CCS 2023 cited by 6